#ifndef _REGUART_H_
#define _REGUART_H_

/* UART [0:2] line control register */

#define S3C2440_REG_ULCON0      0x50000000
#define S3C2440_REG_ULCON1      0x50004000
#define S3C2440_REG_ULCON2      0x50008000

/* UART [0:2] control register */

#define S3C2440_REG_UCON0       0x50000004
#define S3C2440_REG_UCON1       0x50004004
#define S3C2440_REG_UCON2       0x50008004

/* UART [0:2] FIFO control register */

#define S3C2440_REG_UFCON0      0x50000008
#define S3C2440_REG_UFCON1      0x50004008
#define S3C2440_REG_UFCON2      0x50008008 

/* UART [0:1] modem control register */

#define S3C2440_REG_UMCON0      0x5000000C
#define S3C2440_REG_UMCON1      0x5000400C

/* UART [0:2] Tx/Rx status register */

#define S3C2440_REG_UTRSTAT0    0x50000010
#define S3C2440_REG_UTRSTAT1    0x50004010
#define S3C2440_REG_UTRSTAT2    0x50008010 

/* UART [0:2] Rx error status register */

#define S3C2440_REG_UERSTAT0    0x50000014
#define S3C2440_REG_UERSTAT1    0x50004014
#define S3C2440_REG_UERSTAT2    0x50008014 

/* UART [0:2] FIFO status register */

#define S3C2440_REG_UFSTAT0     0x50000018
#define S3C2440_REG_UFSTAT1     0x50004018
#define S3C2440_REG_UFSTAT2     0x50008018

/* UART [0:1] modem status register */

#define S3C2440_REG_UMSTAT0     0x5000001C
#define S3C2440_REG_UMSTAT1     0x5000401C

/* UART [0:2] transmission hold register */

#define S3C2440_REG_UTXH0       0x50000020
#define S3C2440_REG_UTXH1       0x50004020
#define S3C2440_REG_UTXH2       0x50008020

/* UART [0:2] receive buffer register */

#define S3C2440_REG_URXH0       0x50000024
#define S3C2440_REG_URXH1       0x50004024
#define S3C2440_REG_URXH2       0x50008024

/* UART [0:2] baud rate divisor register */

#define S3C2440_REG_UBRDIV0     0x50000028
#define S3C2440_REG_UBRDIV1     0x50004028
#define S3C2440_REG_UBRDIV2     0x50008028

#endif